1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to the cell structure of a dynamic RAM (DRAM), and also to a method of manufacturing the DRAM.
2. Description of the Prior Art
The integrated density of a DRAM, which has memory cells each comprising one MOS transistor and one capacitor, is gradually increasing. The higher the integration density, the smaller the area occupied by the capacitor of each memory cell. The smaller the area of the capacitor, the less charge the capacitor accumulates. Consequently, destruction of the data in the memory cell is more likely to take place.
FIG. 1A is a sectional view of a memory cell array of a conventional DRAM with a trench type capacitor structure.
FIG. 1B shows a plane view of such a memory cell. Line A--A shows the location of the sectional view shown in FIG. 1A.
As shown in FIG. 1A, DRAM cell 1000 is formed on a Si substrate 1001 and it has a MOSFET 1002 and a trench type capacitor 1003 which comprises an SiO.sub.2 layer 1004, a storage node electrode 1005, a capacitor insulating layer 1006, and a plate electrode 1007 in this order.
A part of the storage node electrode 1005 is coupled with one of a source/drain regions 1010 of the MOSFET by a storage node contact 1016. A gate electrode 1011 operates as a word line, 1012 is a bit line. A bit line contact 1013 is shared by two adjacent memory cells. Also, a passing word line 1014 passes over the plate electrode of the trench capacitors. Each cell is isolated by field area 1015 formed by LOCOS method. An arrangement of the trenches of the DRAMs is symmetrical to the shared bit line contact.
However, as shown in FIG. 1A, reducing the memory cell size is limited by the field area 1015 and the array of the cells.
As shown in FIG. 1B, this structure has a possibility that leakage currents may occur between a storage node contact 1016 of the memory cell 1000 and the adjacent memory cell 1017, if the distance t between the adjacent memory cells becomes shorter by increasing the integrated density.
Leakage currents tend to flow from a storage node contact 1016 to other storage node contacts or to the source/drain regions.
Accordingly, the distance t among the adjacent storage node contacts of the memory cell could not be minimized adequately.
Also, there is the possibility of leakage currents caused by narrowing the distance between the storage node contact and the device area of the adjacent cell. The narrowing of the distance may be caused by alignment errors when the storage node contact is patterned, because the contact must be formed by removing a very small part of SiO.sub.2 layer 1004. To prevent leakage currents, a precise alignment and a strict resolving power are needed.
Moreover, in this structure, the step of plate electrode 1007 over the trench capacitors and the LOCOS field area 1015 becomes a dominant cause which leads to interconnections of word lines or bit lines formed afterward. To prevent the problem, the step may be formed by a thinner plate layer. However, this will cause another problem in that the resistivity of the layer is made higher.
Even if the field area 1015 is made by a BOX isolating method, which is a way to form a trench on the substrate and refill the trench with an insulating layer, the problem of the plate electrode step cannot be solved completely.